Conventional integrated circuit wiring utilizes a multilevel structure which is fabricated above the active devices formed on the semiconductor surface. Connections between active devices are achieved through several patterned conducting layers which are connected through vias to one another and to the underlying active circuitry. However, there are inherent process limitations to the number of successive levels of interconnects that can feasibly be implemented. This is due to the layout of the vias and contacts for the upper interconnecting levels which place substantial constraints on the lower interconnect levels and associated active devices.
Conventionally, an active device is first fabricated by defining the active circuitry in the surface of a silicon wafer. Thereafter, an insulating layer is disposed over the substrate and vias formed through the insulating layers to expose selected areas of the active circuitry. A metal interconnecting layer is then formed on the upper surface of the insulating layer with interconnections through the vias to the exposed areas of the active circuitry on the silicon surface. Thereafter, additional levels of insulating layers and metal layers can be disposed to accommodate complex interconnection schemes. The inherent limitations resulting from the layout of the active circuits and the metal interconnecting layers place certain constraints on the number of interconnecting levels that can be utilized. The layout of the active active devices on the semiconductor surface limits the number of successive interconnect levels and more often than not defines the layout constraints for the active circuits.
One solution to the interconnect problem has been to provide a buried interconnecting layer fabricated from a heavily doped region. These buried layers are fabricated in the process by forming a heavily doped region in the substrate and then growing an epitaxial layer over the heavily doped region. The circuit is then defined in the surface of the epitaxial layer and then contacts are made with this buried layer from the surface. However, the buried conductor technology utilizing heavily doped regions has its own inherent limitations.
In view of the above, there exists a need for a method to increase the number of levels of interconnects without unduly complicating the layout of the active devices on the semiconductor surface.